1. Field of the Invention
The invention relates to memory management, and in particular to a hardware apparatus (memory managing IC) and method for managing access of RAS (Row Address Strobe) memory pages by looking ahead to the next task (next device accessing memory) in determining whether to open or close the RAS memory page after the initial access
2. Background Information
There are many patents in the field of memory management. For example, Olson et al., U.S. Pat. No. 4,933,910 "METHOD FOR IMPROVING THE PAGE HIT RATIO OF A PAGE MODE MAIN MEMORY SYSTEM" relates to a method wherein a row address strobe signal is maintained active during an idle cycle so that if a page hit is detected on a subsequent memory cycle, all that is needed to read or write to memory is a column address strobe signal which can be provided via a page mode access (see Abstract, for example). However, this patent does not apparently take into account any considerations to save cycles based on a page miss. This may be shown to be very expensive time-wise since the probability of a page miss, considering context switches, cache misses and drivers, such as used with direct draw, is much greater than 50% as seen by a DRAM controller with a system implementing an L1 and L2 cache, for example.
Pawlowski et al., U.S. Pat. No. 5,301,299 "OPTIMIZED WRITE PROTOCOL FOR MEMORY ACCESS UTILIZING ROW AND COLUMN STROBES" relates to a method for fast page mode accessing of memory. A RAS line, once activated, remains activated even if the bus is idle in anticipation of a DRAM page hit from a subsequent access--the RAS line is held active only if another access is pending and the access is a hit to the same DRAM page as the immediately previous access (see col. 2, lines 1 to 10, for example). While this patent seems to emphasize the importance of optimizing performance for page misses, it only provides performance enhancements for page misses if there is a latency between back-to-back accesses, assuming that if there is no access after completion of the current access, then there will be a page miss. This patent system would apparently experience full setup delays in the case where there are multiple bus masters, a first bus master is currently accessing an open page, and immediately following, another bus master is granted access to a different page. The probability of this happening is high, and increses with the number of bus masters. In another scenario, after a first bus master has accessed an open page, a latency of multiple clocks occurs, followed by a request from another bus master to open the same page, which however, would have already been closed. This can occur with shared buffering and semaphores between two bus masters.
Kametani (1), U.S. Pat. No. 5,335,336 "MEMORY DEVICE HAVING REFRESH MODE RETURNING PREVIOUS PAGE ADDRESS FOR RESUMED PAGE MODE" and Kametani (2), U.S. Pat. No. 5,479,635 "MEMORY DEVICE INCLUDING DRAMS FOR HIGH-SPEED ACCESSING" relate to DRAM organized by page, divided into groups. Means is provided to store an old page address designated at least one access earlier, and for judging whether or not a new page address coincides with the old page address (see Abstract, for example). These patents are apparently specific to page mode, static column mode and nibble mode DRAMs. In addition, they could not apparently be applied to an external memory controller with, for example, X86/Pentium or Pentium-Pro processors, unless both DRAM banks are mapped within the same address space region, since separate memory regions are required for instructions and data access. With most processors, the type of access (instruction or data) cannot always be detected, and although regional in memory, no knowledge of the type of access being performed is defined unless the region is defined within the memory controller. Therefore, the interface must be implemented with a processor that separates the memory map into instruction fetches and data fetches, and defines this as such with some cycles status output.
Goodwin et al. U.S. Pat. No. 5,371,870 "STREAM BUFFER MEMORY HAVING A MULTIPLE-ENTRY ADDRESS HISTORY BUFFER FOR DETECTING SEQUENTIAL READS TO INITIATE PREFETCHING" provides a bank of FIFOs in a memory controller to hold sequential read data for a number of data streams being fetched by a computer. The system detects sequential addresses as a stream, fetches data from DRAM for addresses in sequence, and stores the prefetched data in one of the FIFOs (see Abstract).
Bland et al. U.S. Pat. No. 5,034,917 "COMPUTER SYSTEM INCLUDING A PAGE MODE MEMORY WITH DECREASED ACCESS TIME AND METHOD OF OPERATION THEREOF" relates to a computer system in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS pre-charge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.
Wicklund et al. U.S. Pat. No. 5,159,676 "SEMI-SMART DRAM CONTROLLER IC TO PROVIDE A PSEUDO-CACHE MODE OF OPERATION USING STANDARD PAGE MODE DRAWS" relates to a DRAM controller which uses logic to selectively enable or disable a page mode of operation as a result of specific instructions from executing software, or upon some prediction of page mode efficiency based on past performance. An address multiplexor generates separate row and column addresses from the CPU address control lines, and to generate the necessary signals to control the timing of the RAS and CAS control signals that operate the DRAM. Page mode is automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one.
Mayer et al. U.S. Pat. No. 5,303,364 "PAGED MEMORY CONTROLLER" relates to a computer system having a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories while having a zero wait state page hit operation.
Adams U.S. Pat. No. 5,357,606 "ROW INTERLEAVED FRAME BUFFER" relates to a frame buffer operating in fast page access mode with improved performance for operations such as scrolling and moving which typically access different display memory rows. The system utilizes a row/bank interleaved scheme of multiple display memory banks in the frame buffer such that each display memory bank supports a different set of non-contiguous display rows thus increasing the odds of display memory access in-page hits and decreasing the odds of display memory access in-page misses.
Goodwin et al. U.S. Pat. No. 5,388,247 "HISTORY BUFFER CONTROL TO REDUCE UNNECESSARY ALLOCATIONS IN A MEMORY STREAM BUFFER" relates to a read buffering system employing a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the stream buffer is protected by EDC.
Lin et al. U.S. Pat. No. 5,440,713 "M-WAY N-PORT PAGED-INTERLEAVED MEMORY SYSTEM" relates to a memory access system suitable for use in a computer system having M memory banks and N masters. The memory access system comprises a separate paged interleaved controller associated with each of the M memory banks. Each of the paged interleaved controllers comprises a bank arbiter and a bank controller. The bank arbiter associated with each memory bank receives requests from the N masters and subjects them to a request-halt protocol. The request-halt protocol executed by each arbiter prioritizes among a plurality of current requests by the masters for the same memory bank. Each arbiter insures that a current request generated by a master will not be granted if the master has a previous request that has not been granted by another arbiter. This insures that the requests of each master are granted in the order in which the requests are made. The request-halt protocol gives a higher priority to current requests specifying a row address which is the same as a valid row address of the previous memory request granted by the arbiter. The request-halt protocol prioritizes among current requests if there is no valid row address of a previous request or if no current address specifies a row address which is the same as the valid row address of the previously granted request.
Tatosian et al. U.S. Pat. No. 5,461,718 "SYSTEM FOR SEQUENTIAL READ OF MEMORY STREAM BUFFER DETECTING PAGE MODE CYCLES AVAILABILITY FETCHING DATA INTO SELECTED FIFO, AND SENDING DATA WITHOUT ACCESSING MEMORY" relates to a read buffering system (like Goodwin et al. above) employing a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accessed needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently masks a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential addresses are frequent. One feature is appending page mode read cycles to a normal read, in order to fill the FIFO. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the data in the stream buffer is protected by EDC.
Murdoch et al. U.S. Pat. No. 5,572,692 "MEMORY CONFIGURATION DECODING SYSTEM HAVING AUTOMATIC ROW BASE ADDRESS GENERATION MECHANISM FOR VARIABLE MEMORY DEVICES WITH ROW ACCESS INTERLEAVING" relates to a memory configuration system which includes a memory controller comprising a set of memory configuration registers which store information related to memory devices installed in random access memory. The memory configuration registers correspond to one or more rows of memory banks in the random access memory. The memory controller also includes a row size and mask generator coupled to the memory configuration register set and a memory configuration decoder coupled to the row size and a mask generator. The combination of logic within the row size and mask generator and the memory configuration decoder is used to generate a base address for each row of memory locations within the random access memory. The present invention automatically reconfigures the memory array to define the most populous row as Row 0 regardless of where the largest row is physically populated. The reconfiguration of the memory array is the logical to physical mapping feature provided by the system. The system also provides a default memory configuration means (i.e., default ordering of rows) for performing the logical to physical mapping in a predictable manner when two or more rows are populated with equal amounts of memory.
Kocis et al. U.S. Pat. No. 5,485,589 "PREDICTIVE ADDRESSING ARCHITECTURE" relates to a computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.
Fitch U.S. Pat. No. 5,493,666 "MEMORY ARCHITECTURE USING PAGE MODE WRITES AND SINGLE LEVEL WRITE BUFFERING" relates to a memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allows the processor to be freed before the write is completed for the most frequently occurring type of write operations.
Goodwin et al. U.S. Pat. No. 5,586,294 "METHOD FOR INCREASED PERFORMANCE FROM A MEMORY STREAM BUFFER BY ELIMINATING READ-MODIFY-WRITE STREAMS FROM HISTORY BUFFER" relates to a read buffering system employing FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When a system sees a read command from the CPU, it stores an incremented value of the address of the read command in a history buffer and marks the entry as valid. The system detects a stream when a subsequent read command specifies an address that matches the address value stored in the history buffer. Upon detecting a stream, the system fetches data from DRAMs at addresses that follow the address of the subsequent read command, and stores it in a FIFO. To reduce unnecessary prefetching, the system looks for a read X, write X, read X+1 (where X and X+1 designate addresses) series of commands to prevent them from creating a stream. This succession occurs often and qualifies as a stream, but is seldom followed by other reads that maintain the stream. The system checks for this series by comparing a incremented value of the address of the write commands with each valid address value stored in the history buffer. A match causes the system to invalidate the history buffer entry containing the matched address value. This effectively disables the use of this address value for detecting a stream upon subsequent read commands and, consequently, for prefetching data from memory.
In prior systems, such as some of those described above, if an error is made in keeping a page open, that is, a next device/task memory miss (closed page hit), there is a performance penalty over simply closing the open page after access by a first device. A need exists for optimizing performances of page misses. Therefore, there exists a need for a more accurate determination of the next task's target page.